1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory, and more particularly to nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor.
2. Description of the Related Art
Nonvolatile semiconductor memory array retains stored data when power is removed. Many different types of data cells suitable for nonvolatile memory are known, including a class of single transistor devices that are based on the storage of charge in discrete trapping centers of a dielectric layer of the structure, and another class of devices that are based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide. The trapped charge establishes the threshold voltage, or VT, of the device, which is sensed when the memory is read to determine the data stored therein.
An illustrative well known type of compact floating gate data cell structure is the stacked gate structure such as that disclosed in U.S. Pat. No. 5,357,465, issued Oct. 18, 1994 to Challa. A floating gate is sandwiched between two insulator layers. The top layer of the stack is a control gate electrode. The stacked gate structure overlies a channel region and parts of the source and drain regions adjacent the channel.
As is typical of nonvolatile memory cells that are capable of being repeatedly programmed and erased, the various functions of the stacked gate memory cell are controlled by applying various bias voltages. Depending to some extent on device characteristics, stacked gate transistors may be programmed by moving electrons to the floating gate using Fowler-Nordheim (“FN”) tunneling or electron injection. Electron injection typically is done using channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). FN tunneling remains a popular choice in flash memory for erase operations.
Conventionally, the single transistor cell is operated to store one of two values by having its threshold voltage VT set within one of two levels of VT distribution, as shown in FIG. 1. To read a cell is to compare the threshold voltage of the cell to the threshold voltage of a reference cell. For instance, the data cell is read out as “1” if its threshold voltage is lower than the reference threshold voltage, and is read out as “0” if its threshold voltage is higher than the reference threshold voltage. The voltage margin VM between the two levels of distribution is typically about 3 volts.
FIG. 2 is a block-level schematic diagram showing a prior art bit mapping scheme for the two-level memory cell of FIG. 1. The mapping scheme is a simple 1 to 1 mapping. Each memory cell of the memory cell array 206 selected by the row decoder 202, the column decoder 204, and the column selects 208 maps to one bit. Hence, eight memory cells map to BIT 1, BIT 2, BIT 3, BIT 4, BIT 5, BIT 6, BIT 7 and BIT 8. No mapping circuit is needed.
Techniques are also known for achieving multiple bit storage in a single transistor nonvolatile memory cell by programming the multiple bits into a memory cell as different threshold voltage levels or in different parts of the cell. FIG. 3 shows four levels of VT distribution representing states 0, 1, 2 and 3. The use of four levels per memory cell increases the effective data density of the flash memory array without increasing its die size.
FIG. 4 is a block-level schematic diagram showing a prior art bit mapping scheme for the four-level memory cell of FIG. 3. The mapping scheme is a 1 to 2 mapping. Each memory cell of the memory cell array 406 selected by the row decoder 402, the column decoder 404, and the column selects 408 maps to two bits. Hence, four memory cells map to BIT 1, BIT 2, BIT 3, BIT 4, BIT 5, BIT 6, BIT 7 and BIT 8.
Each selected memory cell is mapped to two bits by a mapping circuit. FIG. 4 shows four mapping circuits 410, 420, 430 and 440 for providing a byte of data. The mapping circuit 410 performs a 1 cell to 2 bit mapping by comparing the threshold voltage of the selected memory cell with three different threshold reference voltages. The comparisons are done in parallel by comparators 412, 414 and 416, which have their inputs connected in parallel to a bit line and provide a value on their outputs that is dependent on the threshold level of the selected memory cell. Levels 0, 1, 2 and 3 may result, for example, in 000, 001, 011 and 111 respectively at the outputs of the comparators 412, 414 and 416. The outputs of comparators 412, 414 and 416 are processed in combinatorial logic circuit 418 to furnish outputs B1 (bit 1 output) and B2 (bit 2 output), the values of which are, for example, 00, 01, 10 and 11 respectively. The output B1 is considered to be BIT 7, and the output B2 is considered to be BIT 8. The mapping circuit 420 functions in a manner similar to the mapping circuit 410 to furnish BIT 5 and BIT 6 from the outputs B1 and B2 of a combinatorial logic circuit 428, which in turn receives the outputs of parallel-connected comparators 422, 424 and 426. The mapping circuit 430 functions in a manner similar to the mapping circuit 410 to furnish BIT 3 and BIT 4 from the outputs B1 and B2 of a combinatorial logic circuit 438, which in turn receives the outputs of parallel-connected comparators 432, 434 and 436. The mapping circuit 440 functions in a manner similar to the mapping circuit 410 to furnish BIT 1 and BIT 2 from the outputs B1 and B2 of a combinatorial logic circuit 448, which in turn receives the outputs of parallel-connected comparators 442, 444 and 446.
Another technique for sensing four-level memory cells is disclosed in U.S. Pat. No. 5,828,616 which issued Oct. 27, 1998 to Bauer et al. and is entitled “Sensing scheme for flash memory with multilevel cells.” This technique of reading a multilevel cell is to compare the threshold voltage of the cell to a sequence of reference cell threshold voltages. Three reference threshold voltages VTR1, VTR2 and VTR3 are established. First, the threshold voltage of the data cell is compared to VTR1. If it is smaller than VTR1, it is next compared with VTR2. Otherwise, it is compared with VTR3. Based on the two consecutive comparisons, the cell is read out as “11” or “10” or “01” or “00”. Disadvantageously, two consecutive comparisons makes the random access time slower for this type of sensing technique, relative to the parallel sensing technique of FIG. 4.
The reliability of memories using four-level memory cells can be adversely affected because of the small voltage margin VM. The voltage margin VM typically is reduced to 0.67 volts from the 3 volt margin common in conventional flash memory cell, assuming that the threshold voltage distribution width for the same state is 0.5 volts. Therefore, the difference between the threshold voltage of a data cell and the reference threshold voltage is only 0.33 volts if the reference threshold voltage is positioned in the middle of the two states. Unfortunately, electron leakage can cause a threshold voltage shift of as much as 0.5 volts, which is in excess of the difference between the threshold voltage of a data cell and the reference threshold voltage and can result in a functional failure.
A variety of memories having multilevel cells are known; see, e.g., U.S. Pat. No. 4,415,992 which issued Nov. 15, 1983 to Adlhock and is entitled “Memory system having memory cells capable of storing more than two states;” U.S. Pat. No. 5,163,021 which issued Nov. 10, 1992 to Mehrotra et al. and is entitled “Multi-state EEPROM read and write circuits and techniques;” U.S. Pat. No. 5,485,422 which issued Jan. 16, 1996 to Bauer et al. and is entitled “Drain bias multiplexing for multiple bit flash cell;” U.S. Pat. No. 5,517,138 which issued May 14, 1996 to Baltar et al. and is entitled “Dual row selection using multiplexed tri-level decoder;” U.S. Pat. No. 5,748,546 which issued May 5, 1998 to Bauer et al. and is entitled “Sensing scheme for flash memory with multilevel cells;” U.S. Pat. No. 5,754,469 which issued May 19, 1998 to Hung et al. and is entitled “Page mode floating gate memory device storing multiple bits per cell;” U.S. Pat. No. 5,828,616 which issued Oct. 27, 1998 to Bauer et al. and is entitled “Sensing scheme for flash memory with multilevel cells;” U.S. Pat. No. 5,982,667 which issued Nov. 9, 1999 to Jyouno et al. and is entitled “Nonvolatile semiconductor memory device for storing multivalue information by controlling erase and plural write states of each memory cell;” U.S. Pat. No. 6,028,792 which issued Feb. 22, 2000 to Tanaka et al. and is entitled “Multi-level memory for verifying programming results;” U.S. Pat. No. 6,052,303 which issued Apr. 18, 2000 to Chevallier et al. and is entitled “Apparatus and method for selecting data bits read from a multistate memory;” U.S. Pat. No. 6,091,631 which issued Jul. 18, 2000 to Kucera et al. and is entitled “Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed;” U.S. Pat. No. 6,181,603 which issued Jan. 30, 2001 to Jyouno et al. and is entitled “Nonvolatile semiconductor memory device having plural memory cells which store multi-value information;” U.S. Pat. No. 6,219,276 which issued Apr. 17, 2001 to Parker et al. and is entitled “Multilevel cell programming;” U.S. Pat. No. 6,259,626 which issued Jul. 10, 2001 to Pasotti et al. and is entitled “Method for storing bytes in multi level nonvolatile memory cells;” U.S. Pat. No. 6,366,496 which issued Apr. 2, 2002 to Torelli et al. and is entitled “Method for programming multi level non-volatile memories by controlling the gate voltage;” and U.S. Pat. No. 6,456,527 which issued Sep. 24, 2002 to Campardo et al. and is entitled “Nonvolatile multilevel memory and reading method thereof.”